On-chip power management

ABSTRACT

The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements: -a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR).

CROSS-REFERENCE TO RELATED APPLICATION(S) AND CLAIM OF PRIORITY

The present application is related to Indian Patent Application No.2771/Del/2008, filed Dec. 5, 2008, entitled “ON-CHIP POWER MANAGEMENT”.Indian Patent Application No. 2771/Del/2008 is assigned to the assigneeof the present application and is hereby incorporated by reference intothe present disclosure as if fully set forth herein. The presentapplication hereby claims priority under 35 U.S.C. §119(a) to IndianPatent Application No. 2771/Del/2008.

TECHNICAL FIELD

The present disclosure relates to power management and, morespecifically, to on-chip power management.

BACKGROUND

In semiconductor technology, rapidly shrinking integrated circuit (IC)dimensions drive the requirement of reduced device geometries resultingin the need for multiple voltages to retain compliance with operationalconstraints. This necessitates the use of on-chip power regulators. Intypical applications, the on-chip power regulator derives the supplyvoltage for the digital core from the input/output (IO) supply voltage.For example, an on-chip regulator generates the 1.2 V supply (for thedigital core) from the 3.3 V supply (of the IOs) to save an extraoff-chip supply and also to reduce the bill of material (BOM) cost.

In order to facilitate testing, the on-chip regulator is oftenenabled/disabled by a control signal. This control signal can either begiven directly from the IO pad (on the IO ring) or can be driven by thedigital core logic itself. However, providing the control signal fromthe IO ring increases the required number of IO pads resulting inincreased cost of packaging.

FIG. 1 illustrates an on-chip control mechanism 100 for on-chip powerregulators. The on-chip regulator is controlled by signals which aregenerated by the digital core. However, since the digital core itself isoperating on the Vdd supply generated by the regulator, this may resultin unreliable system operation. Further, this approach does not allowthe testing of the various sub blocks of the power management unit(PMU).

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of this disclosure and its features,reference is now made to the following description, taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 illustrates a conventional power regulator;

FIG. 2 illustrates a block diagram of a power management deviceaccording to an embodiment of the present disclosure;

FIG. 3 illustrates a power management device according to an embodimentof the present disclosure;

FIG. 4 illustrates the voltage level of signals used in the powermanagement block according to an embodiment of the present disclosure;

FIG. 5 illustrates a block diagram that discloses an application for apower management device according to an embodiment of the presentdisclosure; and

FIG. 6 illustrates a method for providing a stable regulated supplyvoltage according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The embodiments of the present disclosure are described in detail withreference to the accompanying drawings. However, the present disclosureis not limited to these embodiments which are only provided to explainmore clearly the present disclosure to the ordinarily skilled in the artof the present disclosure. In the accompanying drawings, like referencenumerals are used to indicate like components.

The present disclosure teaches a power management device for providingone or more voltages. The power management device prohibits the system'soperation until it has been initialized and the supply voltage isstable. The power management device includes a power regulator blockcapable of being enabled or disabled by one or more control signalsgenerated by the digital logic core and processed in a masking block.The power regulator block includes any one or more of the followingelements—voltage regulator, bandgap reference generator, and low voltagedetector. The masking block includes a plurality of logic gates, and apower on reset circuit (PoR).

The disclosure also teaches an integrated circuit which includes a powermanagement device for providing one or more voltages. The powermanagement device prohibits the system's operation until it has beeninitialized and the supply voltage is stable. The power managementdevice includes a power regulator block capable of being enabled ordisabled by one or more control signals generated by the digital logiccore and processed in a masking block. The power regulator blockincludes any one or more of the following elements—voltage regulator,bandgap reference generator, and low voltage detector. The masking blockincludes a plurality of logic gates, and a power on reset circuit (PoR).

The disclosure further teaches a system which includes a powermanagement device for providing one or more voltages. The powermanagement device prohibits the system's operation until it has beeninitialized and the supply voltage is stable. The power managementdevice includes a power regulator block capable of being enabled ordisabled by one or more control signals generated by the digital logiccore and processed in a masking block. The power regulator blockincludes any one or more of the following elements—voltage regulator,bandgap reference generator, and low voltage detector. The masking blockincludes a plurality of logic gates, and a power on reset circuit (PoR).

The disclosure also teaches a method for providing a stable regulatedsupply voltage. Initially, the input supply voltage is monitored by thePoR circuit, and the system is initialized for safe startup. Once theinput supply voltage and output supply voltage achieve predeterminedvoltage levels, the power management controls are transferred to thedigital logic core. The status of input and output supply voltages areavailable to the system, and once the voltage levels fall below thepredetermined levels, the control is taken back by the power managementdevice.

FIG. 2 illustrates a power management device 200 according to anembodiment of the present disclosure. Power management device 200includes a power regulator block 201 and a masking block 202. Powerregulator block 201 receives an input power supply (IO supply voltage)Vin and provides a regulated power supply voltages at its outputterminal for operation of the digital core and also provides variousstatus signals for input and output supplies. Power regulator block 201is enabled or disabled by one or more control signals received frommasking block 202. Masking Block 202 has one or more input terminals forreceiving the digital signals from the digital logic core andsubsequently provides the control signals to control the power regulatorblock 201.

FIG. 3 illustrates a power management device 300 according to anembodiment of the present disclosure. The power regulator block 201includes a regulator 301, a bandgap reference generator (BGAP) 302, afirst low voltage detector LVDD 303, and a second low voltage detectorLVDM 304. Masking block 202 includes a power on reset circuit 307, aplurality of level shifters 308, a plurality of logic gates 309, a delayblock 306 and a plurality of logic gates 309. In an embodiment, thedelay block 306 is D flip-flop. Regulator (REG) 301 generates the outputvoltage VDDOUT with desired load current capacity for the operation ofthe digital core. Bandgap reference generator 302 generates thereference voltage V_(REF) required by regulator 301, and low voltagedetectors (LVDs) 303 and 304. Low voltage detector (LVDD) 303 checkswhether the digital supply voltage is high enough for the safe operationof the digital logic. Low voltage detector (LVDM) 304 determines whetherthe IO supply voltage is high enough for the safe operation of the IOsand other analog blocks such as a phase-locked loop (PLL), ananalog-to-digital converter (ADC), etc.

Power on reset (PoR) circuit 307 monitors the input voltage V_(in) andgenerates a reset signal nREST when the input voltage V_(in) achievesthe desired level. Power on reset (PoR) circuit 307 is coupled to the Dflip-flop 306 for providing an initial reset signal based on the voltagelevel of the input supply. The initial reset signal nREST is providedfor initializing all the nodes of power management block 300. The Dflip-flop block 306 generates nPUP signal for initializing the digitallogic and the masking block itself.

Low voltage detectors 303, 304 compare a fraction of the voltage levelwith the reference voltage V_(REF). During the startup phase, there is apossibility that low voltage detectors 303, 304 do not get a reliablereference voltage and thus may give a false OK signal at the outputs. Toavoid this problem, the PoR circuit 307 provides the nREST signal whichis used to mask the outputs of low voltage detectors 303, 304. PoRcircuit 307 is designed in such a way that by the time the nREST signalis released, the bandgap reference voltage V_(REF) is available. ThenPUP signal is generated by using the nREST signal and the output signalof low voltage detectors 303, 304. PoR circuit 307 detects the supplylevel V_(in) and maintains nREST signal to a low state until apredetermined threshold is reached, after which the nREST signal ispulled to a high state and follows the input supply level.

Power management device 300 has features for testing each analogfunctional section. After the startup, the REGPD signal is forced high.This forces the on-chip regulator into a power down state, and the 1.2 vdigital voltage is applied externally to the chip. The threshold voltagefor the LVDD 303 is measured by varying the 1.2 v supply externally andmeasuring the LVDDOK signal logic level. A first current consumption(CC1) of the power regulator block includes the current consumptions ofthe LVDM, LVDD, BGAP and PoR blocks. The low voltage detector LVDD 303is powered down by asserting a high LVDDPD signal and determining asecond current consumption (CC2). The second current consumption (CC2)is compared with the first current consumption CC1 of the powerregulator block for calculating the current consumption of LVDD 303.

The threshold voltage for LVDM 304 is measured by varying the IO supplyand checking the LVDMOK signal logic level. Then the low voltagedetector LVDM 304 is placed in power down mode for calculating a thirdcurrent consumption (CC3) of the power regulator block. The thirdcurrent consumption CC3 is compared with the second current consumptionCC2 for calculating the bias current consumption of the LVDM 304.

The bandgap reference generator BGAP 302 is placed in the Power Downmode for measuring a fourth current consumption (CC4) which is the biascurrent for the PoR circuit 307. The fourth current consumption CC4 iscompared the third current consumption CC3 for determining the currentconsumption of the bandgap reference generator BGAP 302. The IO supplyis dropped to lower values such that the nREST/nPUP signal again goeslow. Varying the IO supply level in this manner provides the PoRthresholds.

FIG. 4 illustrates the voltage level of signals used in the powermanagement block according to an embodiment of the present disclosure.At voltage level S1, the IC is initialized and its operation isactivated. The power management controls are transferred to the digitalcore. At voltage level S2, the startup cycle is initiated. The powermanagement controls are taken back from the digital core. Thisillustrates that the IC's operation is active between S1 and S2.

FIG. 5 illustrates a block diagram that discloses an application for apower management device 200, which provides one or more voltages andprohibits the system's operation until it has been initialized and thesupply voltage is stable. System 500 includes the power managementdevice 200 which includes a power regulator block 201 and a maskingblock 202. One embodiment of system 500 is used in automotiveapplications for body control.

Embodiments of the method for providing a stable regulated supplyvoltage are described in FIG. 6. The methods are illustrated as acollection of blocks in a logical flow graph, which represents asequence of operations that can be implemented in hardware, software, ora combination thereof. The order in which the process is described isnot intended to be construed as a limitation, and any number of thedescribed blocks can be combined in any order to implement the process,or an alternate process.

FIG. 6 illustrates the flow diagram of a method for providing a stableregulated supply voltage according to an embodiment of the presentdisclosure. In step 601, the input supply voltage is monitored by thePoR circuit. Once the input supply voltage and the output supply voltageachieve predetermined voltage levels, the nPUP signal is generated andthe power management control is transferred to the digital logic core toensure safe startup. Subsequently, the status of input and output supplyvoltages is provided to the system. Power management control is takenback when supplies fall below the predetermined level for safe powerdown. The predetermined voltage level is based on the systemrequirements. Thus, the regulated supply voltage is disabled wheneverthe input supply voltage is less than a predetermined level as depictedin step 602.

The embodiments of the present disclosure, relating to power managementdevice, are used in various applications, such as inmicrocontroller-based controls. End-use domains include automotiveapplications for body control and power train. The power managementblock provides multiple voltages and also prohibits operation until theIC is initialized and voltage stability is achieved. It provides a safeand robust startup mechanism for an integrated circuit. It does notrequire an external power up signal. The operation of the system doesnot require any startup delays and is not dependent on time delays asall control transfers incorporate handshaking. The testability of analogblocks improves Design For Test (DFT) coverage of the chip, anddebugging is facilitated incase the power management block is notperforming as per the specifications. There is no need for externalcontrol signals and the cost of extra Pads/pins is avoided. The approachallows the use of a bypass mode to check the chip performance withoutthe regulator by supplying the digital voltage externally.

Although the disclosure of system and method has been described inconnection with the embodiment of the present disclosure illustrated inthe accompanying drawings, it is not limited thereto. It will beapparent to those skilled in the art that various substitutions,modifications and changes may be made thereto without departing from thescope and spirit of the disclosure.

The various embodiments described above can be combined to providefurther embodiments. All of the U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet incorporatedherein by reference, in their entirety. Aspects of the embodiments canbe modified, if necessary to employ concepts of the various patents,applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of theabove-detailed description. In general, in the following claims, theterms used should not be construed to limit the claims to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all possible embodiments along with the full scopeof equivalents to which such claims are entitled. Accordingly, theclaims are not limited by the disclosure.

It may be advantageous to set forth definitions of certain words andphrases used in this patent document. The term “couple” and itsderivatives refer to any direct or indirect communication between two ormore elements, whether or not those elements are in physical contactwith one another. The terms “include” and “comprise,” as well asderivatives thereof, mean inclusion without limitation. The term “or” isinclusive, meaning and/or. The phrases “associated with” and “associatedtherewith,” as well as derivatives thereof, may mean to include, beincluded within, interconnect with, contain, be contained within,connect to or with, couple to or with, be communicable with, cooperatewith, interleave, juxtapose, be proximate to, be bound to or with, have,have a property of, or the like.

While this disclosure has described certain embodiments and generallyassociated methods, alterations and permutations of these embodimentsand methods will be apparent to those skilled in the art. Accordingly,the above description of example embodiments does not define orconstrain this disclosure. Other changes, substitutions, and alterationsare also possible without departing from the spirit and scope of thisdisclosure, as defined by the following claims.

1. A system comprising a power management device, said power managementdevice comprising: a power regulator block having its input coupled toan input power supply and its outputs providing one or more regulatedpower supply voltages, said power regulator block is configured to beenabled or disabled by one or more control signals; and a masking blockhaving at least one input coupled to a digital signal and its outputscoupled to said control signals.
 2. The system as claimed in claim 1,wherein said power regulator block comprises one or more elementsselected from a group comprising: a band gap reference generator; a lowvoltage detector; and a voltage regulator.
 3. The system as claimed inclaim 1, wherein said masking block comprises: a power on reset circuit;and one or more logic units configured to generate said control signals.4. The system as claimed in claim 3, wherein said power on reset circuitis configured to monitor the voltage of said input power supply and togenerate a reset signal when said voltage is at a desired level.
 5. Thesystem as claimed in claim 1, wherein said power management device isconfigured to prohibit an operation of said system until said powermanagement device has been initialized and the supply voltage is stable.6. An integrated circuit comprising a power management device, saidpower management device comprising: a power regulator block having itsinput coupled to an input power supply and its outputs providing one ormore regulated power supply voltages, said power regulator block capableof being enabled or disabled by one or more control signals; and amasking block having at least one input coupled to a digital signal andits outputs coupled to said control signals.
 7. The integrated circuitas claimed in claim 6, wherein said power regulator block comprises oneor more elements selected from a group comprising: a band gap referencegenerator; a low voltage detector; and a voltage regulator.
 8. Theintegrated circuit as claimed in claim 6, wherein said masking blockcomprises: a power on reset circuit; and one or more logic unitsconfigured to generate said control signals.
 9. The integrated circuitas claimed in claim 8, wherein said power on reset circuit is configuredto monitor the voltage of said input power supply and to generate areset signal when said voltage is at a desired level.
 10. The integratedcircuit as claimed in claim 6, wherein said power management device isconfigured to prohibit an operation of said integrated circuit untilsaid power management device has been initialized and the supply voltageis stable.
 11. A power management device comprising: a power regulatorblock having its input coupled to an input power supply and its outputsproviding one or more regulated power supply voltages, said powerregulator block capable of being enabled or disabled by one or morecontrol signals; and a masking block having at least one input coupledto a digital signal and its outputs coupled to said control signals. 12.The device as claimed in claim 11, wherein said power regulator blockcomprises one or more elements selected from a group comprising: a bandgap reference generator; a low voltage detector; and a voltageregulator.
 13. The device as claimed in claim 11, wherein said maskingblock comprises: a power on reset circuit; and one or more logic unitsconfigured to generate said control signals.
 14. The device as claimedin claim 13, wherein said power on reset circuit is configured tomonitor the voltage of said input power supply and to generate a resetsignal when said voltage is at a desired level.
 15. The device asclaimed in claim 11, wherein said power management device is configuredto prohibit an operation of a system until said power management devicehas been initialized and the supply voltage is stable.
 16. A method forproviding a stable regulated supply voltage, said method comprising:monitoring an input supply voltage; and disabling said regulated supplyvoltage whenever said input supply voltage is less than a predeterminedlevel.
 17. The method as claimed in claim 16, further comprisingproviding an initial reset signal based on the voltage level of theinput supply voltage.
 18. The method as claimed in claim 16, furthercomprising generating a reset signal nREST when said input supplyvoltage is at or above the predetermined level.
 19. The method asclaimed in claim 16, wherein the input supply voltage is monitored by apower on reset circuit.
 20. The method as claimed in claim 16, whereinsaid regulated supply voltage is disabled by one or more control signalsgenerated by a digital logic core.